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1

50 Years of CORDIC: Algorithms, Architectures, and Applications

Meher, P.K., Valls, J., Tso-Bing Juang, Sridharan, K., Maharatna, K.

Journal:

IEEE Transactions on Circuits and Systems I: Regular Papers

Year:

2009

Language:

english

File:

PDF, 755 KB

english, 2009

2

[IEEE 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008 - Seattle, WA, USA (2008.05.18-2008.05.21)] 2008 IEEE International Symposium on Circuits and Systems - A novel VLSI iterative divider architecture for fast quotient generation

Tso-Bing Juang,, Sheng-Hung Chen,, Shin-Mao Li,

Year:

2008

Language:

english

File:

PDF, 124 KB

english, 2008

3

[IEEE 2014 International Symposium on Integrated Circuits (ISIC) - Singapore (2014.12.10-2014.12.12)] 2014 International Symposium on Integrated Circuits (ISIC) - Fast binary to BCD converters for decimal communications using new recoding circuits

Juang, Tso-Bing, Chiu, Yu-Ming

Year:

2014

Language:

english

File:

PDF, 192 KB

english, 2014

4

[IEEE 2015 International SoC Design Conference (ISOCC) - Gyungju, South Korea (2015.11.2-2015.11.5)] 2015 International SoC Design Conference (ISOCC) - New recoding methods for fully pipelined parallel CORDIC rotations

Juang, Tso-Bing, Chiu, Chin-Chieh

Year:

2015

Language:

english

File:

PDF, 174 KB

english, 2015

5

[IEEE 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - Pittsburgh, PA, USA (2016.7.11-2016.7.13)] 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) - Seamlessly Pipelined Shift-and-Add Circuits Based on Precise Delay Analysis and Its Applications

Juang, Tso-Bing, Lee, Ying-Ren

Year:

2016

Language:

english

File:

PDF, 296 KB

english, 2016

6

Improved Area-Efficient Weighted Modulo Adder Design With Simple Correction Schemes

Tso-Bing Juang, Chin-Chieh Chiu, Ming-Yu Tsai

Journal:

IEEE Transactions on Circuits and Systems II: Express Briefs

Year:

2010

Language:

english

File:

PDF, 365 KB

english, 2010

7

A Lower Error and ROM-Free Logarithmic Converter for Digital Signal Processing Applications

Tso-Bing Juang, Sheng-Hung Chen, Huang-Jia Cheng

Journal:

IEEE Transactions on Circuits and Systems II: Express Briefs

Year:

2009

Language:

english

File:

PDF, 539 KB

english, 2009

8

Corrections to “VLSI Design of Diminished-One Modulo Adder Using Circular Carry Selection” [Sep 08 897-901]

Tso-Bing Juang, Ming-Yu Tsai, Chin-Chieh Chiu

Journal:

IEEE Transactions on Circuits and Systems II: Express Briefs

Year:

2009

Language:

english

File:

PDF, 184 KB

english, 2009

9

[IEEE APCCAS 2012-2012 IEEE Asia Pacific Conference on Circuits and Systems - Kaohsiung, Taiwan (2012.12.2-2012.12.5)] 2012 IEEE Asia Pacific Conference on Circuits and Systems - A lower error antilogarithmic converter using novel four-region piecewise-linear approximation

Kuo, Chao-Tsung, Juang, Tso-Bing

Year:

2012

Language:

english

File:

PDF, 471 KB

english, 2012

10

[IEEE 2013 International Soc Design Conference (ISOCC) - Busan, South Korea (2013.11.17-2013.11.19)] 2013 International SoC Design Conference (ISOCC) - High-speed binary to binary-coded-decimal converters for decimal multiplications

Juang, Tso-Bing, Chiu, Yu-Ming

Year:

2013

Language:

english

File:

PDF, 215 KB

english, 2013

11

[IEEE 2012 International SoC Design Conference (ISOCC 2012) - Jeju Island, Korea (South) (2012.11.4-2012.11.7)] 2012 International SoC Design Conference (ISOCC) - Parallel and digit-serial implementations of area-efficient 3-Operand Decimal Adders

Tso-Bing Juang,, Hsin-Hao Peng,, Han-Lung Kuo,

Year:

2012

Language:

english

File:

PDF, 162 KB

english, 2012

12

[IEEE 2000 Southwest Symposium on Mixed-Signal Design - San Diego, CA, USA (2000.02.27-2000.02.29)] 2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390) - Discussions on the CORDIC processor using leading zeros detector

Tso-Bing Juang,, Shen-Fu Hsiao,

Year:

2000

Language:

english

File:

PDF, 170 KB

english, 2000

13

[IEEE 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Hsinchu, Taiwan (2011.04.25-2011.04.28)] Proceedings of 2011 International Symposium on VLSI Design, Automation and Test - High-performance logarithmic converters using novel two-region bit-level manipulation schemes

Juang, Tso-Bing, Meher, Pramod Kumar, Jan, Kai-Shiang

Year:

2011

Language:

english

File:

PDF, 148 KB

english, 2011

14

Low Latency Angle Recoding Methods for the Higher Bit-Width Parallel CORDIC Rotator Implementations

Juang, Tso-Bing

Journal:

IEEE Transactions on Circuits and Systems II: Express Briefs

Year:

2008

Language:

english

File:

PDF, 266 KB

english, 2008

15

[IEEE 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Hsinchu, Taiwan (2011.04.25-2011.04.28)] Proceedings of 2011 International Symposium on VLSI Design, Automation and Test - Efficient weighted modulo 2n+1 adders by partitioned parallel-prefix computation and enhanced circular carry generation

Juang, Tso-Bing, Meher, Pramod Kumar, Chiu, Chin-Chieh

Year:

2011

Language:

english

File:

PDF, 178 KB

english, 2011

16

[IEEE APCCAS 2010-2010 IEEE Asia Pacific Conference on Circuits and Systems - Kuala Lumpur, Malaysia (2010.12.6-2010.12.9)] 2010 IEEE Asia Pacific Conference on Circuits and Systems - Area-efficient parallel-prefix Ling adders

Juang, Tso-Bing, Meher, Pramod Kumar, Kuan, Chung-Chun

Year:

2010

Language:

english

File:

PDF, 183 KB

english, 2010

17

[IEEE APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - Singapore (2006.12.4-2006.12.7)] APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - Area/Delay Efficient Recoding Methods for Parallel CORDIC Rotations

Juang, Tso-Bing

Year:

2006

Language:

english

File:

PDF, 117 KB

english, 2006

18

[IEEE 2002 IEEE Asia-Pacific Conference on ASIC. - Taipei, Taiwan (6-8 Aug. 2002)] Proceedings. IEEE Asia-Pacific Conference on ASIC, - A high performance function generator for multiplier-based arithmetic operations

Tso-Bing Juang,, Jeng-Hsin Jan,, Ming-Yu Tsai,, Shen-Fu Hsiao,

Year:

2002

Language:

english

File:

PDF, 241 KB

english, 2002

19

[IEEE 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC) - Kowloon, Hong Kong (2011.10.3-2011.10.5)] 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip - Area-efficient 3-input decimal adders using simplified carry and sum vectors

Tso-Bing Juang,, Hsin-Hao Peng,, Chao-Tsung Kuo,

Year:

2011

Language:

english

File:

PDF, 1002 KB

english, 2011

20

MULTIFUNCTION RNS MODULO 2 n ± 1 MULTIPLIERS

JUANG, TSO-BING, KUO, CHAO-TSUNG, WU, GO-LONG, HUANG, JIAN-HAO

Journal:

Journal of Circuits System and Computers

Year:

2012

Language:

english

File:

PDF, 1.00 MB

english, 2012

21

[IEEE APCCAS 2012-2012 IEEE Asia Pacific Conference on Circuits and Systems - Kaohsiung, Taiwan (2012.12.2-2012.12.5)] 2012 IEEE Asia Pacific Conference on Circuits and Systems - Multifunction RNS modulo (2n±1) multipliers based on modified booth encoding

Juang, Tso-Bing, Huang, Jian-Hao

Year:

2012

Language:

english

File:

PDF, 571 KB

english, 2012

22

[IEEE The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. - Tainan, Taiwan (Dec. 6-9, 2004)] The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. - Low-error carry-free fixed-width multipliers and their application to DCT/IDCT

Tso-Bing Juang,, Shen-Fu Hsiao,, Shiann-Rong Kuang,, Ming-Yu Tsai,

Year:

2004

Language:

english

File:

PDF, 274 KB

english, 2004

23

Lower-error and area-efficient antilogarithmic converters with bit-correction schemes

Juang, Tso-Bing, Kuo, Han-Lung, Jan, Kai-Shiang

Journal:

Journal of the Chinese Institute of Engineers

Year:

2016

Language:

english

File:

PDF, 739 KB

english, 2016

24

[IEEE APCCAS. Asia-Pacific Conference on Circuits and Systems - Bali, Indonesia (28-31 Oct. 2002)] Asia-Pacific Conference on Circuits and Systems - Partition methodology for the final adder in a tree-structure parallel multiplier generator

Tso-Bing Juang,, Jeng-Hsiun Jan,, Ming-Yu Tsai,, Shen-Fu Hsiao,

Year:

2002

Language:

english

File:

PDF, 350 KB

english, 2002

25

Design of fast logarithmic converters with high accuracy for digital camera application

Kuo, Chao-Tsung, Juang, Tso-Bing

Journal:

Microsystem Technologies

Year:

2016

Language:

english

File:

PDF, 718 KB

english, 2016

26

[IEEE 2016 International SoC Design Conference (ISOCC) - Jeju, South Korea (2016.10.23-2016.10.26)] 2016 International SoC Design Conference (ISOCC) - Low-cost concurrent error detection schemes for logarithmic converters

Juang, Tso-Bing, Lee, Ying-Ren, Chiu, Chin-Chieh

Year:

2016

Language:

english

File:

PDF, 167 KB

english, 2016

27

[IEEE 2017 International SoC Design Conference (ISOCC) - Seoul (2017.11.5-2017.11.8)] 2017 International SoC Design Conference (ISOCC) - Low-area implementations of concurrent error detection logarithmic processors

Juang, Tso-Bing, Lee, Ying-Ren

Year:

2017

Language:

english

File:

PDF, 292 KB

english, 2017

28

[IEEE 2019 International SoC Design Conference (ISOCC) - Jeju, Korea (South) (2019.10.6-2019.10.9)] 2019 International SoC Design Conference (ISOCC) - Design of High-Speed and Area-Efficient Cartesian to Polar Coordinate Converters Using Logarithmic Number Systems

Juang, Tso-Bing, Lin, Cong-Yi, Lin, Guan-Zhong

Year:

2019

File:

PDF, 212 KB

2019